Logic circuits that must operate across power disruptions are known to the art. The simplest form of such circuits utilizes some form of energy storage such as a battery to maintain the state of the system during the period in which the power that normally runs the circuit is off. Such systems are limited by the amount of power that can be stored. Some circuitry prolongs the period over which external power is not needed by entering a low power mode that maintains the state of the circuitry for an extended period of time.
A second class of circuits stores the state of the system in a non-volatile memory prior to powering down in the event of a power disruption. When power is restored, the system state is “reloaded” from the non-volatile memory and system operation continues. This type of system typically requires a separate save/restore mode. In one class of systems, the non-volatile memory that stores the state operates at different logic levels or frequencies than the circuitry whose state is being saved. For example, the non-volatile memory could be an EEPROM that operates as a shadow RAM. The voltages and cycle times needed to store information into the non-volatile memory are substantially different from those used by the logic circuits, and hence, the non-volatile memory cannot track the state of the system in real time such that the state of the system is always stored in the non-volatile memory. In addition, the save cycle requires a separate system mode that adds complexity and cost to the system.
A second class of non-volatile memory is based on ferroelectric memory devices. These devices operate at the same logic levels as the other circuitry, and can be read and written in times comparable to those of the logic circuitry. However, these non-volatile memory devices must be read and written synchronously, and hence, using such non-volatile memory devices for storing and restoring the state of the system still typically involves a separate save/restore procedure. Further, since these memories can be written by voltages that are within the normal logic levels of the associated circuitry, preventing alteration of the data stored therein during periods of power instability such as during power down or power up poses significant challenges.